How PCB Fabrication process drives DFM Guidelines

Key Process Tolerances that Affect Registration

  • Photoimaging
    • Inner Layers, Pattern Plating, Solder mask, and Silk Screen
    • Front to back +/-2mil
    • Layer to Layer +/3mil
    • Etching solutions undercut dry film and tin, so artwork has to be enlarged on lines/pads to achieve desired sizes
  • Etching
    • Cores, sub lamination outer layers, final outer layers
    • Cores relax when Cu is removed, so artwork has to be compensated, up to +/-3mil
      • Based on previous runs and similar designs; Predictive, but not exact
  • Lamination
    • Sub-laminations and final lamination
    • Pins holding stacks of material have approx. +/-1mil tolerance to the bushings
    • Prepregs melt and settle when glass weaves nest
      • Epoxy flows into etched Cu gaps on cores and sub-lamination layers
  • Tooling Holes & Drilling
    • Drills bits +/0.0005mil
    • Post-etch punch drills holes in cores to hold during lamination +/-1mil
    • Bushings used in caul plates during lamination +/1mil or more, if damaged
    • X-ray drill optimizes locations and drills the holes used to hold panel during drilling +
    • Drill to drill +/-3mil
    • Drill tooling holes are also used for fabrication (route or V-score)
    • X-ray drill may also scale or compensate the whole drill pattern to fit the fiducials
    • Pattern plating and solder mask artwork need to be adjusted accordingly
  • Routing
    • Standard tolerance +/-5mil
    • Optical routing tolerance +/-2mil
  • Misalignment of Copper Patterns to Holes, Solder Mask, and Legend In
    • Drill to copper +/-2mil
    • Standard LPI +/-3mil, LDI  +/-1.5-2mil
PCB Fabrication process

Key Process Tolerances

PCB Fabrication process


Material Characteristics that Affects Design Minimums

  • Cu foil and Laminates have thickness tolerances
    • Cu foil tolerance +/- 10%, plus process reduction for inner layers
    • Thin core tolerances > +/-10
  • Laminate & prepreg expansion & shrinkage during processing
    • Supported with glass weave
    • Cores used for I/L may shrink during etch
    • Unsupported moves all over the place
  • Expansion of material during drill
    • Diameters after drill may be smaller than the drill bits
    • Disruption of fiberglass weaves allow wicking; may exceed min space requirements
  • Plated through-holes are drilled at FHS + .1mm or 4-5mil, reducing Drill Hole Wall to copper feature distances
    • Plated through-hole , PTH FHS tolerance = +/-3mil,
    • Via tolerance +3mil/-Finished Hole Size (planned for drill bit/pad diameters)
    • Non-plated through-hole, NPTH FHS = +/-2mil
    • Press-fit and compliant pin specifications often wrong between starting drill bit and FHS
    • Conforming plated pin holes tolerance = +/-2mil
    • Dry film used to protect Cu during etch requires artwork compensation
    • Fabricator increase linewidths based on Cu thickness, which reduces available space
PCB Fabrication process

Single Lamination Mechanical Drills

  • Conventional Through Hole
  • >0.65mm BGA
  • Min .008” drill
  • 4mil line/space
  • 10:1 aspect ratio
Single Lamination Mechanical Drills

Multiple Lam Mech Drills

  • Blind Vias
  • Buried Vias
  • Through Hole
  • Min .008” drill
  • 10:1 Aspect Ratio
  • Lamination cycles= press + drill + plate
  • Significant cost
Multiple Lam Mech Drills

Heavy Copper PCB

  • > 2oz. Cu foil
  • Up to 12 oz. Inner Layers
  • High Voltage/Amps
  • Single or multiple lam
  • Increased lines/spaces for etch capability
  • Special-order material
  • Increases cost & lead time
Heavy Copper PCB

Standard HDI  PCB with > 0.4mm BGA

  • 4mil laser micro Vias
  • 10mil pads
  • Offset Micro Vias
  • 3mil min lines
  • 1 or more lams
  • Offset micro Vias
  • Stacked micro Vias
Standard HDI  PCB with > 0.4mm BGA

Micro HDI ≤ 0.4mm BGA

  • 3-4mil laser micro Vias
  • 8.8mil pads
  • 2.3mil lines/spaces
  • Stacked micro Vias
  • Multiple lam cycles
Micro HDI ≤ 0.4mm BGA

RF & Microwave PCB

  • Advanced materials
  • Cavities
  • Horizontal Launch
  • Filters , antennas
  • Controlled etch
  • Hybrid stack-ups
  • Multiple lam cycles
RF & Microwave PCB

Determine the PCB Technology Requirements:

Fabricators’ site qualification quick-check at time of design or quote, Smallest, densest component determines the stack-up

  1. Manufacturing Panel Utilization (how many PCBs fit on the master panel)
  2. Performance Class (IPC-6012D Class 2, 3, A, or MIL-PRF-55110/31032)
  3. Layer Count (total number of required cores) #cores = (#Layers-2)/2
  4. Type of dielectric Material (Standard or RF, lead time, processing complications)
  5. Number of Lamination Cycles – each cycle requires lam/drill/plate/etch est.+25% per lam cycle
  6. HDI (via-in-pad, multiple lam cycles, requires enabling equipment)
  7. Design Complexity –

Line Widths and Feature Spacing

  • 4/4mil STD, 3/3mil +23-30%, 2.5/2/5mil +50% require LDI
    • Controlled Impedance (CI) requirement & tolerance
      • 10%CI STD, 7%CI +20%, 5%CI +30% (if process-capable)
    • Drilled Hole Size (Aspect Ratio = PCB Thickness: Drill Diameter)
    • 25K drills/panel STD, extra 10K +1-2%, +15-20%
    • Laser drilled microvias
    • Requires special plating process
  • Overall PCB Thickness (Equipment Limitations)/ Aspect Ratios
    • <10:1 STD, 10-11.99:1 +10-15%, 12-12.99:1 +20-25%
  • Annular Ring Requirements vs Design (Registration Capabilities)
  • Copper Weights (Cost, Availability, and impact on Etching)
  • Special requirements (routed cavities, castellations, edge plating, controlled depth drill, back-drill, solder mask plugged Vias, or VIPPO)
  • Process Yield (often a Hidden Cost based on DFM violations!)

Micro HDI Requires Enabling Equipment

2.5 – 3mil lines/spaces is a technology limiter, based on fabricator etch capabilities

Laser Direct Imaging

Laser Direct Imaging

Laser Microvia Drilling 4 – 6mil diameter

Laser Microvia Drilling 4 – 6mil diameter

Reverse Pulse Plating Process

Reverse Pulse Plating Process

Vacuum Etching for <2.5mil lines/spaces

Vacuum Etching for <2.5mil lines/spaces

Key Process Tolerances that Determine Design Minimums

  • Lamination, Standard thickness tolerance +/-10%
  • Drilling
    • (Minimum drill to copper (avoid shorts and CAF, > 8mil))
      • Required due to misregistration of materials and processes
      • Layer to Layer +/-3mil
      • Front to back imaging +/-2mil
      • Drill to drill +/-3mil
      • Drill to copper registration +/-2mil
      • (Annular ring, Classes 1, 2 (90 degree break-out)  and 3 (min a/r 2mil outer, 1mil inner))
        • Dependent on hole to pad size
        • Required due to misregistration
Key Process Tolerances that Determine Design Minimums

Plating (Aspect Ratio = ratio of thickness to drill diameter, ≤10:1 for through-holes)

  • Ability to effectively plate Cu in the hole walls
  • Aspect Ratio of Microvia holes <0.75:1

Etching (Minimum Linewidths +/-20% & Spaces <20% reduction Classes 2/3)

  • Based on Cu thickness being etched
Key Process Tolerances that Determine Design Minimums

Outer/Plated layer thicknesses include base Cu foil plus thickness of plated Cu

  • VIPPO adds an extra layer of plating to base Cu foil; may require slight increase in linewidths on outer layers
  • Fabrication
    • Routing
    • V-score
Key Process Tolerances that Determine Design Minimums

Minimum Mechanical Drill to Copper

Standard (Mechanical Drills) = 0.008” (200 µm) Drill-to-Copper (now .0075”)

  • Imaging  –  Front-to-Back  =  +/- 0.002” (50 µm)
  • Lamination  –  layer-to-layer registration = +/- .003” (75 µm)
  • Drill  –  Drill tolerance = +/- 0.003” (75 µm)

Total Tolerance = 0.008” (200 µm)

Advanced (Mechanical Drills) = 0.0065” (165 µm) Hole-to-Copper – Verify advanced guidelines in ASIA by site (.007” min)

  • LDI Imaging  –  Front-to-Back  =  +/- 0.0015” (25 µm)
  • Lamination  –  layer-to-layer registration = +/- .003” (75 µm)
  • Drill  –  Drill tolerance = +/- 0.002” (50 µm)

Total Tolerance = 0.0065” (150 µm)

LDI Imaging

Plating Process & Aspect Ratio

Aspect Ratio = Ratio of Thickness to Drill bit diameter – Reduced A/R facilitates better Cu plating in the holes

Example 1. Mechanically drilled through hole that will be used to penetrate the entire thickness of the PCB or a through hole that will be used in a mechanically drilled sub-lamination used to form blind or buried Vias.  In this configuration the depth of the hole is measured from the surface of the external copper layers.  In this case if the hole diameter was 0.010” and the depth was 0.093” the Aspect Ratio would be 9.3 to 1.

Max PTH Aspect Ratio:  10 to 1

Mechanically drilled

Example 2.  Laser drilled microvias are a controlled depth hole that terminates on a copper layer.  As a result, the depth of the hole is calculated from the top of the terminating layer to the top of the copper foil layer on the hole entrance.  In this case if the hole diameter was 0.006” and the depth was 0.003” the Aspect Ratio would be 0.5 to 1.

Max Blind Aspect Ratio:  0.75-0.8 to 1

Laser drilled

Understand Drill Types and Annular Ring Requirements

Mechanical Through-holes versus Blind Laser Microvias

  • Mechanical drills are used through stacks of layers and some controlled depth drills
  • Laser drills are used to create BLIND holes, starting at an outer layer and ending on an inner layer, requiring short drill depth to maintain <0.75:1* aspect ratio
  • Laser microvias are NOT used to drill top to bottom through a stack of layers
  • A design with a 5 or 6mil drill in a 10mil pad through all layers is not mass production- worthy
  • A <14* or 16mil* pad diameter should be verified with the Production Supplier for any mechanically drilled through-hole <7.9mil if high volume production quantities are required


VIPPO  adds extra Cu plating before etch


Strip photo resist leaving exposed background copper with pattern plated copper image protected with a tin lead resist

Routing – Minimum Edge-to-Cu Clearance

Standard Route = 0.012” (305 µm) Minimum Edge-to-Copper

Advanced Route = 0.010” (254 µm) Minimum Edge-to-Copper

Imaging – Front-to-Back = +/- 0.002” (50 µm)

Lamination – layer-to-layer registration = +/- .003” (75 µm) Route tolerance = +/- 0.005” (125 µm)

*Total Tolerance = 0.010” (254 µm)

Routing - Minimum Edge-to-Cu Clearance

Optical Route tolerance = 0.002” (50 µm), but still allow 0.010” Min Edge-to-Copper due to other misregistration opportunities

*Routing after component assembly tolerance = +/-.005” (125 um)

Routing - Minimum Edge-to-Cu Clearance


Normal Web = 1/3 X Thickness, 0.040” example If the V-Score depth = .012”,  then the Score Width with ‘zero’ wear = .006” =.003”/PCB

Leaves .007” Score to Copper

If the V-Score depth = .012”, then the Score Width with ‘max’ wear = .015” = .0075”/PCB

Leaves .0025” Score to Cu*

*Not including other Cu misregistration tolerances up to +/-.005”


Score Depth
Score Width
(At Zero tip wear)
(30 degree blade)
Score Width
(At max tip wear)
(30 degree blade)

Cerra Systems Printed Circuit Board Fabrication capabilities support high-frequency PCB, High-temperature Boards, Thick PCB, ultra-thin PCB, heavy copper PCB, Metal Core PCB, HDI boards with Blind Vias, Buried Vias, Micro Vias, Embedded passives, bonded heat sink, Impedance Control, Depth control drilling, Back drilling, Edge Plated PCB, Bump Pads, cavity with ledge, Via on pad and stacked micro-Via technology.

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