PCB Fabrication Cost Drivers: Impedance Control, Via plugging, Finish

PCB Cost Drivers

PCB Fabrication Cost Drivers | PCB Fabrication in India

•  Impedance adders

  •    +/-10% tolerance is considered standard
  •    +/-7% tolerance adds ~20% (~10% in Asia)
  •    +/-5% tolerance adds ~30%
  •    These values are dependent upon original line widths, whether or not the tight toleranced lines are on plated layers,
  •    Paying for the tightened impedance tolerance may be of no benefit if the proposed stack up and the material set is not robust
  •    Etching tolerances are independent of line widths and using wider lines improved tolerances can be obtained
      • A 0.1 mil line width difference on a 3 mil 50 Ohm line equals 6%
      • A 0.1 mil line width difference on a 5 mil 50 Ohm line equals 9%

• Soldermask

  • Glossy or matte solder mask – No cost adder
  • Different solder mask colors – 0-5% depending on quantity/region

               –   Use caution with black or white solder mask (capability and yield issues)

  • LDI solder mask adder – 10-20% depending on panel quantity/region
  • The cost adder for different solder masks is due to having to break down the set-up for one color to use another
  • Silk-screening is a batch process and is set up for each particular work order/part number
  • For customers that use different solder mask colors to identify RoHS or lead-free products in their manufacturing process, consider using a different silkscreen color instead as a more cost-effective option

•  Via plugging

    • No cost adders for any via plugging or button printing of vias 18 mils (0.457mm) or less using solder mask in North America
    • For Asia, cost adders are BP=3-5%, VP=7%, full SM fill=8-10%
    • Plugging of vias >18 mil (drilled) requires design review
    • Tenting of vias is unreliable, as it is hoped that the solder mask, a very thin viscous liquid, will span holes and not collapse
    • Tented holes will break, and can entrap solution, leading to corrosion of copper and premature failure
    • The best approaches, in order of fabricator preference, are as follows:
      • Leave the vias completely open from both sides
      • Leave vias open during finishing and apply a tent to one side (“button print”)
      • Plug them completely and then tent over with a solder mask (“via plug”)

•  Finishing adders

  • OSP, silver, tin, ENIG, and leaded HASL are no-cost adders for North
  • For ASIA, HASL & OSP no-cost adders, Immun. Ag 2-3%, Immun. Sn 5-10% & ENIG 10-19%.
  • ENEPIG adds 5% per manufacturing panel (subcontract is higher)
  • Lead-free HASL adds 5% per manufacturing panel (subcontract is higher)
  • Hard gold is priced per in2 area and the current market cost of gold
  • Selective finishes are priced as per design review

•  Miscellaneous adders

  •  Scoring – No cost adder
  • Milling – 5-10% (at +/-5 mil tolerance)
  • Counterbores and countersinks (non-plated) – No cost adder
  • Counterbores and countersinks (plated) – 5-10%
  • Edge plating – 5-10% (plus additional costs associated with reduced #up on the manufacturing panel)
  • Back drill – ~5% per drill size
  • Castellations (half holes on edge) – 5-15% depending on size/density
  • Cavities – Avoid if possible! (Cost dependent on design)

 

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